module top (
    input clk,
    input rst_n,
    output tx_data,
    output tx_valid,
    input rx_data,
    input rx_valid
);

// Some instances with normal connections
submodule_a u_sub_a (
    .clk(clk),
    .rst_n(rst_n),
    .data_out(tx_data),
    .valid_out(tx_valid)
);

// Instance that might cause "wire" parsing issue
problematic_module u_prob (
    .clk(clk),
    .rst_n(rst_n),
    .data_out(wire),  // This could cause "wire" to appear as port name
    .valid_out(rx_valid)
);

endmodule

module submodule_a (
    input clk,
    input rst_n,
    output data_out,
    output valid_out
);

assign data_out = 1'b0;
assign valid_out = 1'b0;

endmodule

module problematic_module (
    input clk,
    input rst_n,
    output data_out,
    output valid_out
);

assign data_out = 1'b1;
assign valid_out = 1'b1;

endmodule